The present invention relates to a nonvolatile semiconductor memory device in which write is executed by means of channel hot electrons and an erase method therefor.
Conventionally, there has been an ETOX (EPROM THIN OXIDE: trademark of Intel Corp.) as a flash memory (batch erase type memory) used most generally. FIG. 12 shows a schematic sectional view of this ETOX type flash memory cell 8. As is apparent from FIG. 12, a floating-gate 5 is formed via a tunnel oxide film 4 on a source 1, a drain 2 and a substrate (well) 3 located between the source and the drain. Further, a control gate 7 is formed on the floating-gate 5 via a layer insulation film 6.
The principle of operation of the ETOX type flash memory cell 8 will now be described. As shown in the following Table 1, during write, a voltage Vpp (10 V, for example) is applied to the control gate 7, a reference voltage Vss (0 V, for example) is applied to the source 1, and a voltage of 6 V is applied to the drain 2. With this arrangement, a large amount of current flows through the channel layer to generate channel hot electrons in a portion of a high electric field on the drain 2 side, and the electrons are injected into the floating-gate 5. Consequently, the threshold voltage of the memory cell 8 rises to execute write into the memory cell 8. FIG. 13 shows threshold voltage distributions in a written state and an erased state. As shown in FIG. 13, the threshold voltage of the written memory cell 8 becomes equal to or higher than 5 V.
During erase, by applying a voltage Vnn (xe2x88x929 V, for example) to the control gate 7, applying a voltage Vpe (6 V, for example) to the source 1 and making the drain 2 open, intense electric field occurs in the tunnel oxide film 4 located between the source 1 and the floating-gate 5. Then, electrons are extracted from the floating-gate 5 toward the source 1 by the Fowler-Nordheim (FN) tunneling phenomenon, lowering the threshold voltage of the memory cell 8. Consequently, as shown in FIG. 13, the threshold voltage of the erased memory cell 8 becomes 1.5 V to 3 V.
During read, a voltage of 1 V is applied to the drain 2, and a voltage of 5 V is applied to the control gate 7. In this case, when the memory cell 8 is in the erased state and has a low threshold voltage, a current flows through the memory cell 8 to determine that the state is xe2x80x9c1xe2x80x9d. When the memory cell 8 is in the written state and has a high threshold voltage, no current flows through the memory cell 8 to determine that the state is xe2x80x9c0xe2x80x9d.
On the basis of the principle of operation as described above, the write, erase and read of the memory cell 8 are executed. During the erase of the actual nonvolatile semiconductor memory device, the erase is executed in batch processing of comparatively large blocks of, for example, 64 kB. In the above case, the threshold voltages of the memory cells inside the block to be erased include those in the written state (threshold voltage is not lower than 5 V in FIG. 13) and those in the erased state (threshold voltage is 1.5 V to 3 V in FIG. 13), which exist in a mixed state. Then, in order to put the threshold voltages of all the memory cells 8 that are to be erased within a specified threshold voltage distribution (1.5 V to 3 V, for example), a complicated algorithm is used for the batch erase.
During erase, it is a key point to prevent the occurrence of a memory cell in an overerased (excessively erased) state in which the threshold voltage becomes equal to or lower than 0 V due to the application of an erase pulse to a memory cell that originally has a low threshold voltage and the application of an erase pulse to a memory cell in which the threshold voltage is lowered fast due to variations in erase characteristics.
Upon the occurrence of the memory cell in the overerased state, if it is attempted to apply a specified voltage (3.0 V, for example, in the case of erase verify) to the word line connected to the control gate 7 of the selected memory cell while setting a voltage of 0 V on the word line connected to the control gate 7 of the non-selected memory cell during, for example, write verify or erase verify and to execute verify based on the presence or absence of a cell current flowing through the non-selected memory cell, then a cell current flows also through the memory cell in the overerased state that exists among the non-selected memory cells. Therefore, it is unable to correctly verify the presence or absence of a cell current in the selected memory cells. That is, since the threshold voltage cannot be verified, the write and erase cannot correctly be executed. Therefore, if the memory cell in the overerased state occurs, then the reliability of the nonvolatile semiconductor memory device is impaired.
FIG. 14 shows one example of the erase algorithm for preventing the occurrence of the memory cell in the overerased state. When the erase operation is started in FIG. 14, pre-erase write for preventing the overerase is first executed in all the memory cells in step S1. This pre-erase write operation is the same as the ordinary write operation described hereinabove and executed as follows. That is, the voltages shown in Table 1 are applied to the sources 1 and the substrates (wells) 3 of all the memory cells 8 in the block to be subjected to erase. Then, the memory cells 8 are sequentially selected for the application of the voltages shown in Table 1 to the control gates 7 and the drains 2.
In step S2, the write verify is executed. That is, the threshold voltage value of each memory cell 8 is verified. It is determined in step S3 whether or not the verify result is acceptable, i.e., it is determined whether or not the threshold voltage values of all the memory cells 8 are not lower than the specified value (5.0 V) that represents the written state. As a result, the program flow returns to the step S1 to repeat the pre-erase write when it is unacceptable or proceeds to step S4 when it is acceptable. In this case, the write verify operation has the same application voltages to the drain 2, the source 1 and the substrate (well) 3 as in the read operation in Table 1 and also has an application voltage of 5.0 V to the control gate 7. Thus, the voltage of 5.0 V is applied via the word line to the control gate 7 of the selected memory cell 8 in which the write verify is executed, while a voltage of 0 V is applied to the control gate 7 of the non-selected memory cell 8 to determine whether or not a cell current flows through the selected memory cell 8. Then, it is determined that the threshold voltage of the selected memory cell 8 is not lower than 5.0 V and the written state is established when no cell current flows through the selected memory cell 8. In contrast to this, when a cell current flows, it is determined that the threshold voltage of the selected memory cell 8 is lower than 5.0 V, and the pre-erase write is executed again. Subsequently, this operation is repeated, and the pre-erase write is ended when the threshold voltages of all the memory cells to be erased become equal to or higher than 5.0 V.
In step S4, the erase pulse is applied. The pulse width of the erase pulse in the above case is set to, for example, 10 ms, which is shorter than the erase time required for changing the written state into the erased state so that a number of memory cells, in which the threshold voltage is lowered fast attributed to the variations in the erase characteristics, is not put into the overerased state. Then, by putting the drain 2 of the memory cell 8 to be subjected to erase into an open state, making the substrate (well) 3 have a voltage of 0 V, applying an erase pulse of xe2x88x929 V to the control gate 7 and applying an erase pulse of 6 V to the source 1, the erase is executed in blocks.
The erase verify is executed in step S5 so as to verify whether or not the threshold voltage of the erased memory cell has a specified value. The erase verify operation has the same application voltages to the drain 2, the source 1 and the substrate (well) 3 as in the read operation in Table 1 and has only a varied application voltage of 3.0 V to the control gate 7. Thus, by applying a voltage of 3.0 V via the word line to the control gate 7 of the selected memory cell 8 in which the erase verify operation is executed and applying a voltage of 0 V to the control gate 7 of the non-selected memory cell, it is determined whether or not a cell current flows through the selected memory cell. Then, if a cell current flows through the selected memory cell, then it is determined that the threshold voltage of the selected memory cell is not lower than 3.0 V and the erased state is established. In contrast to this, it is determined that the threshold voltage of the selected memory cell is higher than 3.0 V when no cell current flows.
It is determined in step S6 whether or not the verify result is acceptable, i.e., it is determined whether or not the threshold voltages of all the memory cells are not higher than the specified value (3.0 V) that represents the erased state. As a result, the program flow returns to the step S4 to repeat the application of the erase pulse when it is unacceptable or proceeds to step S7 when it is acceptable. Thus, all the memory cells in the block to be subjected to erase are made to have a threshold voltage of not higher than 3.0 V while alternately executing the application of the erase pulse of the aforementioned pulse width and the verify of the threshold voltage by the erase verify.
In this case, one example of a change in the threshold voltage with respect to an erase pulse applying time is shown in FIG. 15 as an example of the erase characteristics of the memory cell 8. In FIG. 15, when the erase pulse is applied for only 300 ms, a threshold voltage Vt of the memory cell 8 in which the threshold voltage Vt is lowered most rapidly (fast cell) is 1.5 V, and the threshold voltage Vt of the memory cell 8 in which the threshold voltage Vt is lowered most slowly (slow cell) is 3.0 V, depending on the variations in the erase characteristics.
In the case of the memory cells that have the aforementioned erase characteristics, it is determined that the threshold voltage Vt is not higher than 3.0 V (threshold voltage Vt of the slow cell is 3.0 V) through the erase verify with regard to all the memory cells to be erased. On the other hand, the threshold voltage Vt of the fast cell becomes 1.5 V when the erase pulse application ends, and therefore, the distribution of the threshold voltages Vt of all the memory cells in the erased state falls within a range of 1.5 V to 3.0 V.
In step S7, overerase verify for verifying whether or not a memory cell in the overerased state exists is executed. This overerase verify operation has the same application voltages to the source 1 and the substrate (well) 3 as in the read operation in Table 1, and an application voltage of 0 V to the control gate 7 is different from that in the read operation in Table 1. Thus, by applying a voltage of 0 V to all the control gates 7 and applying a voltage of 1 V via the bit line to the drain 2 of the selected memory cell in which the overerase verify is executed, it is determined whether or not a cell current flows through the bit line terminal. Then, if no cell current flows, then it is determined that there is no memory cell in the overerased state among the plurality of memory cells whose drains are connected to the bit line. Then, a voltage of 1 V is applied to the next bit line to execute the overerase verify of the memory cell relevant to the bit line. In this case, if a cell current flows, then it is determined that there is a memory cell in the overerased state among the plurality of memory cells whose drains are connected to the bit line.
It is determined in step S8 whether or not the verify result is acceptable. The program flow proceeds to step S9 when at least one memory cell in the overerased state is consequently detected, or otherwise the erase processing operation is ended when no such memory cell exists. In step S9, soft write (slight write) is executed in the memory cell in the overerased state. This soft write operation is to apply voltages to the source 1 and the substrate (well) 3 of the memory cell similarly to the write operation in Table 1. Then, this operation is executed by sequentially applying the same voltage as that of the write operation in Table 1 to the drain 2 and a voltage of 6 V to the control gate. Then, the overerase verify is executed again, and it is determined that all the memory cells in the overerase state have disappeared if no cell current flow is detected on the bit line. If a cell current flow is detected, then the soft write is executed again. Thus, the soft write and the overerase verify are alternately continued until no cell current is detected. Then, if no cell current becomes detected in the step S8, then the erase processing operation is ended.
Fundamentally, the nonvolatile semiconductor memory device in the initial state normally has a threshold voltage distribution in the erased state in FIG. 13. Therefore, even if the threshold voltage is verified by the next overerase verify, the memory cell in the overerased state is not practically found, and the soft write for putting the overerased state back into the erased state is not executed. However, if a memory cell that has a threshold voltage Vt of not higher than 0 V is found as a consequence of the execution of the overerase verify, then the aforementioned soft write is to be executed.
The above has described the fundamental example of the erase algorithm for preventing the occurrence of the memory cell in the overerased state shown in FIG. 14.
Next, it is tried to estimate the total erase time required for the erase operation shown in FIG. 14 and obtain a occupancy ratio of the pre-erase write time with respect to the total erase time. In this case, the pre-erase write operation is executed according to the normal write operation shown in Table 1 as described above. When the power voltage Vcc of the nonvolatile semiconductor memory device is 5 V, a write pulse (for example, a pulse of 10 V applied to the control gate 7) is generated by a boosting use charge pump circuit provided inside on the basis of this voltage of 5 V. In the above case, the output capability of the boosting use charge pump circuit or the like enables simultaneous write of eight memory cells corresponding to one byte.
Assuming that the time of write into one memory cell is 2 xcexcs, then a time required for the pre-erase write of 64 kB in one block is expressed by the equation (1):                               2          ⁢                      xe2x80x83                    ⁢          μ          ⁢                      xe2x80x83                    ⁢          s          xc3x97          64          ⁢                      xe2x80x83                    ⁢          k          xc3x97                      8            ÷            8                          =                              2            ⁢                          xe2x80x83                        ⁢            μ            ⁢                          xe2x80x83                        ⁢            s            xc3x97            64            xc3x97            1024                    =                      131            ⁢                          xe2x80x83                        ⁢                          ms              .                                                          (        1        )            
Further, a time required for the erase verify to be executed after the pre-erase write is about 90 ms.
Next, the erase pulse (pulse width: 10 ms) is applied while executing the erase verify. In the above case, the total pulse applying time is about 300 ms, and the total erase verify time is about 180 ms. Finally, a time required for the overerase verify is about 90 ms.
With regard to the soft write, the variations in the erase characteristics of the normal nonvolatile semiconductor memory device are shown in FIG. 15 as described above, and therefore, the soft write is not often executed. Therefore, a time required for the soft write is not estimated here. It is to be noted that the time required for the soft write is determined depending on the number of memory cells in the overerased state.
Therefore, the total erase time is about 791 ms, which is the sum of the pre-erase write time (131 ms), the write verify time (about 90 ms), the total pulse applying time (about 300 ms), the total erase verify time (about 180 ms) and the overerase verify time (about 90 ms). Moreover, the pre-erase write time is 131 ms, and therefore, the occupancy ratio of the pre-erase write time with respect to the total erase time becomes about 16%.
In this case, the pre-erase write, which is the same operation as the normal write, has a fast write speed. However, the written state is established with the threshold voltage raised by injecting channel hot electrons from the drain 2 side into the floating-gate 5, and therefore, the consumption of current is large. Therefore, if the power voltage Vcc of the nonvolatile semiconductor memory device is lowered to a voltage of, for example, 3.0 V or 2.4 V or further to 1.8 V, then this pre-erase write time is increased.
FIG. 16 shows this situation. It can be understood from FIG. 16 that, when the power voltage Vcc of the nonvolatile semiconductor memory device is lowered, the number of memory cells (number of bits) in which the pre-erase write can be concurrently executed is reduced, and the time required for the pre-erase write in the memory cells of 64 kB is increased.
The above means that the current consumed during the pre-erase write has a large value of 50 xcexcA per memory cell (one bit) in the case of the pre-erase write that uses channel hot electrons. Therefore, when the power voltage Vcc is lowered, the current supply capability of the boosting charge pump circuit that generates each write pulse through boosting from this power voltage Vcc is reduced, and the number of memory cells in which the write can be executed at a time is reduced.
As shown in FIG. 16, it is possible to execute the pre-erase write concurrently in eight memory cells when the power voltage Vcc=5 V. However, when the power voltage Vcc=1.8 V, the concurrent write can be executed in only one memory cell. As a result, in contrast to the fact that the pre-erase write time in the memory cells of 64 kB in one block is 131 ms when Vcc=5 V as described above, the time is increased to 1048 ms when Vcc=1.8 V. Therefore, the total erase time when Vcc=1.8 V becomes 1708 ms, and this means that the occupancy ratio of the pre-erase write time with respect to the total erase time amounts up to about 61%.
In view of the above, it has become an important factor to reduce the pre-erase write time in order to reduce the total erase time for the reduction in voltage and the integration of the nonvolatile semiconductor memory device expected in the future.
There has been proposed a flash erase type nonvolatile memory of which the pre-erase write time is shortened with an erase method therefor (Japanese Patent Laid-Open Publication No. HEI 10-64288). FIG. 17 shows a circuit block diagram, and FIG. 18 shows a flowchart of the pre-erase write processing operation. In the flash erase type nonvolatile memory shown in FIG. 17, when an erase mode is designated by an input/output signal IO, a pre-erase write and verify period signal WVP from an internal sequence control section 11 rises. The initial value of the address of the memory cell array 14 is set to the least significant address by an internal address generating circuit 12 (step S11), and decoding is executed by a decoding section 13. Then, a pre-erase write control signal PW from the internal sequence control section 11 comes to have an active level, and the pre-erase write at the least significant address of the memory cell array 14 is executed by a write circuit 15. The pre-erase write will be executed while sequentially incrementing an address IAD (steps S12 through S14). When the pre-erase write at the most significant address is ended, a last address detection signal EAD is outputted from the internal address generating circuit 12. Then, a first-time pre-erase write end signal FWE from a first-time write recognizing circuit 16 comes to have an active level, and a verify control signal VF from the internal sequence control section 11 comes to have an active level. Thus, the verify is executed sequentially from the least significant address by a verify circuit 17 (steps S15, S16, S19 and S20). Then, if the result is defective, the pre-erase write control signal PW comes to have an active level, and the rewrite is executed by the write circuit 15 (steps S17 and S18).
Thus, when the pre-erase write is ended, the erase pulse application is started by the internal address generating circuit 12 and an erase circuit 18.
However, the aforementioned prior art flash erase type nonvolatile memory in which the pre-erase write time is shortened and the erase method thereof have the following problems. That is, the flash erase type nonvolatile memory is provided with the first-time write recognizing circuit 16, by which the first-time pre-erase write is executed first in all the memory cells and the rewrite is executed in only the memory cells of the defective write found through the process of executing the verify. By this operation, the pre-erase write time can be further shortened in comparison with the erase algorithm shown in FIG. 14 to repetitively execute the pre-erase write and the verify in one-byte units.
However, there is no change of the fact that the current consumed during the pre-erase write has a very large value of 500 xcexcA. Therefore, if the power voltage Vcc is lowered, then the current supply capability of the boosting charge pump circuit that generates each write pulse through boosting from this power voltage Vcc is reduced. Therefore, the problems that the number of memory cells in which the write can be executed at a time is reduced and the pre-erase write time of the memory cells of 64 kB in one block becomes long are not solved at all.
Accordingly, the object of the present invention is to provide a nonvolatile semiconductor memory device capable of reducing the pre-erase write time that increases as the operating voltage is lowered and consequently reducing the erase time and an erase method therefor.
In order to achieve the aforementioned object, this invention provides a nonvolatile semiconductor memory device in which floating-gate field-effect transistors that respectively have a control gate, a floating-gate, a drain and a source and are able to electrically write and erase information are arranged in a matrix form on a substrate or a well with a plurality of row lines connected to the control gates of the floating-gate field-effect transistors arranged in a direction of row and with a plurality of column lines connected to the drains of the floating-gate field-effect transistors arranged in a direction of column and in which the floating-gate field-effect transistors that constitute a block have their sources connected to a common source line, wherein
the floating-gate field-effect transistors, which belong to an erase object division to be subjected to batch erase, are divided into n (positive integer) regions, and
comprising: for each erase object division,
an erase frequency storage means for storing an erase frequency of the erase object division;
an address setting means for setting addresses of regions which belongs to the erase object division and in which pre-erase write is executed on the basis of storage contents of the erase frequency storage means;
a flag means for storing flag information that represents the erase frequency reaching n every time the erase frequency of the erase object division reaches n; and
an erase frequency resetting means for resetting the storage contents of the erase frequency storage means when the flag information is stored in the flag means.
According to the above-mentioned construction, when the erase is executed in an arbitrary erase object division to be subjected to erase, the erase frequency is stored in the erase frequency storage means corresponding to the erase object division to be subjected to erase. Then, the address of the region in which the pre-erase write is executed is set on the basis of the storage contents of the erase frequency storage means by the address setting means, and the pre-erase write is executed in the set region during erase corresponding to the erase object division. This operation is subsequently repeated. When the erase frequency of the erase object division becomes n, the flag information is stored in the flag means, and the storage contents of the erase frequency storage means is reset by the erase frequency resetting means.
Therefore, the pre-erase write is executed in only the floating-gate field-effect transistors of 1/n of the erase object division every one erase operation corresponding to the erase object division to be subjected to erase. As a result, the pre-erase write time during one erase operation becomes 1/n of that of the prior art, and the total erase operation time is consequently shortened. Thus, the increase in the erase time is prevented, even if the operating voltage is reduced.
In one embodiment, the erase object division is the block.
According to this embodiment, the prevention of the increase in the erase time ascribed to the reduction in the operating voltage is applied to a block erase system nonvolatile semiconductor memory device.
In one embodiment, the erase object division is a memory cell array comprised of the floating-gate field-effect transistors arranged in a matrix form, and
the division into n regions of the erase object division is executed in the blocks.
According to this embodiment, the prevention of the increase in the erase time ascribed to the reduction in the operating voltage is applied to a full-chip erase system nonvolatile semiconductor memory device.
In one embodiment, the erase frequency storage means is comprised of (nxe2x88x921) nonvolatile semiconductor memories.
In one embodiment, the nonvolatile semiconductor memories that constitute the erase frequency storage means have a structure identical to that of the floating-gate field-effect transistors arranged in a matrix form.
According to these embodiments, reset by the erase circuit resetting means can be executed concurrently with the erase of the floating-gate field-effect transistor by applying the erase pulse to the nonvolatile semiconductor memory that constitutes the erase frequency storage means concurrently with the application of the erase pulse to the floating-gate field-effect transistor arranged in a matrix form. That is, it is enabled to concurrently use the erase circuit of the floating-gate field-effect transistor arranged in a matrix form as the erase circuit resetting means.
One embodiment comprises an erase control means for operating, when an erase operation of an arbitrary erase object division is started, to read the (nxe2x88x921) nonvolatile semiconductor memories that constitute the erase frequency storage means corresponding to the erase object division and operating, when any unwritten nonvolatile semiconductor memory or memories exist, to execute write in one of the nonvolatile semiconductor memories and operating, when all the nonvolatile semiconductor memories are in a written state, to store the flag information into the flag means.
According to this embodiment, the erase control means makes the erase frequency storage means store the erase frequency of the erase object division. Furthermore, every time the erase frequency of the erase object division becomes n, the flag means exactly stores the flag information.
This invention also provides an erase method for a nonvolatile semiconductor memory device in which floating-gate field-effect transistors that respectively have a control gate, a floating-gate, a drain and a source and are able to electrically write and erase information are arranged in a matrix form on a substrate or a well with a plurality of row lines connected to the control gates of the floating-gate field-effect transistors arranged in a direction of row and with a plurality of column lines connected to the drains of the floating-gate field-effect transistors arranged in a direction of column and in which the floating-gate field-effect transistors that constitute a block have their sources connected to a common source line, the erase method comprising the step of:
executing pre-erase write in only floating-gate field-effect transistors of 1/n (nxe2x89xa72) of the floating-gate field-effect transistors that belong to an erase object division to be subjected to batch erase.
According to the above-mentioned invention, the pre-erase write is executed in only the floating-gate field-effect transistors of 1/n of the erase object division every one erase operation corresponding to an arbitrary erase object division. Therefore, the pre-erase write time during one erase operation becomes 1/n of that of the prior art, and the total erase operation time is consequently shortened. Thus, the increase in the erase time ascribed to the reduction in the operating voltage is prevented.
In one embodiment, the erase object division is the block.
According to this embodiment, the prevention of the increase in the erase time ascribed to the reduction in the operating voltage is applied to a block erase method.
In one embodiment, the erase object division is a memory cell array comprised of the floating-gate field-effect transistors arranged in a matrix form, and
the floating-gate field-effect transistors in which the pre-erase write is executed are set in the blocks.
According to this embodiment, the prevention of the increase in the erase time ascribed to the reduction in the operating voltage is applied to a full-chip erase method.
In one embodiment, the 1/n floating-gate field-effect transistors are set by dividing the erase object division into n regions, and
the pre-erase write is executed in only one region out of the n regions that constitute the erase object division during one erase operation for the erase object division.
According to this embodiment, the pre-erase write to 1/n of the floating-gate field-effect transistors that belong to the erase object division is executed in units of regions obtained by dividing the erase object division into n regions.
In one embodiment, the n regions that constitute the erase object division are assumed to be a region 0 through a region (nxe2x88x921),
the pre-erase write is executed in only the region 0 during a (nxc2x7k (k: 0 or positive integer)+1)th erase operation,
the pre-erase write is executed in only the region 1 during a (nxc2x7k+2)th erase operation, and
the pre-erase write is executed sequentially to a region (nxe2x88x921) until a (nxc2x7k+n)th erase operation.
According to this embodiment, every time the erase operation is executed in an arbitrary erase object division, the pre-erase write is executed serially in the n regions obtained by dividing the erase object division.
In one embodiment, the pre-erase write is executed in only one region selected from regions of a least pre-erase write frequency out of the n regions that constitute the erase object division.
According to this embodiment, every time the erase operation is executed in an arbitrary erase object division to be subjected to erase, the pre-erase write is executed sequentially in the n regions obtained by dividing the erase object division.